The use of multiple layers of chips provides the opportunity to form very dense electronic circuitry with a very high rate of communication between chips in the stack. The key problem has been to provide wiling to interconnect the chips and for external contact.
In one well known chip stacking structure, transfer wires embedded in insulation on the planar surface of each chip of the stack extend between chip circuits and one edge of the chip, these chip edges forming a side face of the stack. Stacks of adhesively bonded together chips have these chip edges aligned. Large T-connect pads for interconnection and external connection are located on that side face contacting ends of those transfer wires.
Because the chips may vary significantly in thickness and alignment, and because the adhesive and insulation between chips may vary in thickness, the position of a transfer wire end on the side face is uncertain. The uncertainty has made quite difficult the traditional photolithographic semiconductor processing method of using a mask to open contact through an insulator to all desired locations on the side face at once.
One proposed solution, described in U.S. Pat. No. 4,525,921, to Carsen et al. (the '921 Patent), was to selectively etch the silicon on the side face, thereby leaving tips of transfer wires extending beyond the etched silicon surface. A side face insulator, such as polyimide, was then deposited and polished back to expose the tips of transfer wiling for electrical contact. Now, metal could be deposited and T-connect pads photolithographically formed without risk of shorting to conductive edges of the silicon chips since the conductive silicon surface was covered by the side face insulator. A problem with the solution of the '921 Patent was that the silicon-polyimide interface was seriously eroded by the silicon etch, leaving a gap therebetween creating significant downstream processing problems. In addition, the process exposed for contact, not just the desired transfer wire but all metal layers that happened to be along the chip edge, including lower level kerf metal layers. The T-connect pads next deposited tended to short all these metal layers together.
An alternative proposed solution, shown in U.S. Pat. No. 5,478,781 to Bertin et al., formed a via in insulation on the edge of each chip of the stack. Significant attention was needed in opening this via to avoid exposing lower levels of metal and bare silicon edges of the chips during the steps to expose and contact the transfer wires. The spacing and alignment variations necessitated (1) the addition of thicker insulation between stacked chips, (2) the use of extra masking steps on the chip planar surface at wafer level, and (3) extra photoexposure and masking steps on the side face of the stack to avoid opening contact to kerf metal and conductive chip edges. In addition, the use of thicker insulation between chips added significantly to mechanical problems in providing for external contact because polymeric insulation, such as polyimide, has a thermal expansion coefficient much greater than that of silicon.
Thus, a better solution is needed that provides a lower cost and more reliable method of forming contact pads at the ends of each transfer wire on the side face of the stack, the contacts well insulated from the silicon substrates and kerf metal, and this solution is provided by the following invention.